AI's Real Limit: Chip Startup Raises $135M, Bets on Memory Over Compute

Each query directed at an AI model like ChatGPT initiates a complex data journey: information exits memory, undergoes preprocessing by a CPU, travels to a GPU for intensive computation, and then returns. This entire circuit repeats for every single word the AI generates, highlighting a fundamental inefficiency.

This structural bottleneck necessitates routing through some of the industry's most costly and power-hungry chips with every request. Addressing this inefficiency is the core mission of XCENA, a four-year-old startup operating from South Korea and the U.S. The company has engineered a chip that integrates compute capabilities much closer to DRAM—the high-speed, short-term memory chips actively used by processors—enabling routine data operations to be handled near memory, thereby eliminating expensive round trips between CPUs, GPUs, and memory.

Should this technology scale successfully, its impact on AI infrastructure costs could be profound, a factor that largely fuels significant investor enthusiasm. Reflecting this confidence, XCENA recently secured $135 million in a Series B funding round, valuing the company at $570 million and bringing its total capital raised to $185 million.

XCENA CEO Jin Kim co-founded the startup in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim, all of whom are veterans from Samsung and SK Hynix, major memory suppliers to companies like Nvidia. "CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that," Kim stated in an interview with TechCrunch. He added, "The recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures." This sentiment is underscored by the fact that Samsung, SK Hynix, and Micron, the three dominant global memory chip manufacturers, each surpassed a trillion-dollar valuation for the first time this month.

XCENA's business strategy is built on the premise that "inference isn’t just a compute problem; it’s increasingly a memory scaling problem," as articulated by Kim.

The company's innovative chip, the MX1, connects to the CPU via CXL (Compute Express Link), acting as a dedicated high-speed pathway between the processor and memory. It processes data directly within the memory module, before it ever needs to leave, effectively bringing compute to the data rather than the other way around. XCENA asserts that workloads previously requiring ten servers could potentially be managed by just one using their technology.

Kim further explained, "While GPUs excel at matrix multiplication—the heavy math behind AI model training—much of the surrounding data orchestration, including preprocessing, KV cache management [the system that stores prior conversation context so a model doesn’t have to reprocess it], and data caching, still runs on CPUs. Our chip handles those tasks directly within the memory module itself."

With demand for memory solutions surging since the latter half of last year, the company believes market timing is significantly in its favor.

While discussions with several global memory vendors are in their preliminary stages, Kim refrained from disclosing specific names. XCENA's ideal clientele includes hyperscalers who invest tens of billions annually in AI infrastructure, where even a minor improvement in memory efficiency can translate into hundreds of millions in savings.

Currently, the MX1 is in its prototype phase. Mass production of the chips is slated to commence on Samsung’s foundry lines by the close of 2026, with XCENA anticipating revenue generation to begin in 2027.

Unlike neural processing unit (NPU) manufacturers who aim to challenge Nvidia for AI training workloads, XCENA strategically targets the memory-intensive layer that underpins all AI operations.

XCENA identifies Astera Labs and Marvell, both Nasdaq-listed companies focusing on next-generation memory connectivity, as its closest competitors. Kim acknowledges Marvell as a large, established player in the same domain but emphasizes that XCENA's differentiator lies in its intellectual property. "We have thousands of cores," Kim stated, noting that Marvell’s approach, based on public specifications, relies on a comparatively smaller number of general-purpose cores.

These specialized cores are engineered on RISC-V, an open-source chip design architecture, and are optimized for data processing, with each core meticulously designed for small size and high efficiency. Beyond the cores, XCENA undertakes the design of its own internal memory hierarchy, interconnect bus, and DRAM controller—a degree of vertical integration that most chip companies, even larger rivals, typically outsource.

The Series B funding round was co-led by Seoul-based VC firms Altinum and IMM Investment, alongside Corstone Asia, with continued support from existing investors SBI Investment and Mirae Asset Capital. With over 90 employees across offices in Pangyo, a technology hub near Seoul, and Sunnyvale, California, XCENA is also actively engaged in discussions with international investors regarding additional funding.